Field of the Disclosure
The present disclosure relates generally to processors and more particular to memory coherency for processors.
Description of the Related Art
As processors have scaled in performance, they have increasingly employed multiple processing elements, such as multiple processor cores, multiple processing units (e.g., one or more central processing units integrated with one or more graphics processing units), and the like. To enhance processing efficiency, reduce power, and provide for small device footprints, a processor typically employs a memory hierarchy wherein the multiple processing elements share a common system memory and are each is connected to one or more dedicated memory units (e.g., one or more caches). The processor enforces a memory coherency protocol to ensure that different processing elements do not concurrently modify data assigned to a shared memory location at their respective dedicated memory units. To comply with the memory coherency protocol, the processing elements transmit coherency messages (i.e., coherency probes and probe responses) over a communication fabric of the processor. However, in processors with a large number of processing elements, the relatively high number of coherency messages can consume an undesirably large portion of the communication fabric bandwidth, thereby increasing the power consumption and reducing the efficiency of the processor.